IEEE Transactions on Computers
Network flows: theory, algorithms, and applications
Network flows: theory, algorithms, and applications
A clustering-based optimization algorithm in zero-skew routings
DAC '93 Proceedings of the 30th international Design Automation Conference
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Impact of interconnect variations on the clock skew of a gigahertz microprocessor
Proceedings of the 37th Annual Design Automation Conference
Cycle time and slack optimization for VLSI-chips
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Approximation algorithms
Clock Scheduling and Clocktree Construction for High Performance ASICS
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
An Enhanced Multilevel Algorithm for Circuit Placement
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Navigating registers in placement for clock network minimization
Proceedings of the 42nd annual Design Automation Conference
Power Analysis of Rotary Clock
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Integrated placement and skew optimization for rotary clocking
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A clock power model to evaluate impact of architectural and technology optimizations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gated clock routing for low-power microprocessor design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Accurate estimation of global buffer delay within a floorplan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Custom topology rotary clock router with tree subnetworks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
PEEC based parasitic modeling for power analysis on custom rotary rings
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Implementing multiphase resonant clocking on a finite-impulse response filter
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The clock distribution network is a key component of any synchronous VLSI design. High power dissipation and pressure volume temperature-induced variations in clock skew have started playing an increasingly important role in limiting the performance of the clock network. Rotary clocking is a novel technique which employs unterminated rings formed by differential transmission lines to save power and reduce skew variability. Despite its appealing advantages, rotary clocking requires flip-flop locations to match predesigned clock skew on rotary clock rings. This requirement poses a difficult chicken-and-egg problem which prevents its wide application. In this paper, we propose an integrated placement and skew scheduling methodology to break this hurdle, making rotary clocking compatible with practical design flows. A network flow based flip-flop assignment algorithm and a cost-driven skew optimization algorithm are developed. We also present an integer linear programming formulation that minimizes maximum capacitance loaded at any of the rotary rings, thereby maximizing the operating frequency. Experimental results on benchmark circuits show that our method can reduce the tapping cost (measured as the total length of the wire segments connecting the rotary rings to the clock sinks) for rotary clocking by 33%-53%.