Algebraic multigrid theory: The symmetric case
Applied Mathematics and Computation - Second Copper Mountain conference on Multigrid methods Copper Mountain, Colorado
Analytical placement: A linear or a quadratic objective function?
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
Multilevel circuit partitioning
DAC '97 Proceedings of the 34th annual Design Automation Conference
The ISPD98 circuit benchmark suite
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Trading quality for compile time: ultra-fast placement for FPGAs
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
A multigrid tutorial: second edition
A multigrid tutorial: second edition
Performance driven multiway partitioning
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Improved algorithms for hypergraph bipartitioning
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
An effective congestion driven placement framework
Proceedings of the 2002 international symposium on Physical design
Physical hierarchy generation with routing congestion control
Proceedings of the 2002 international symposium on Physical design
Mongrel: hybrid techniques for standard cell placement
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Multilevel optimization for large-scale circuit placement
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A novel net weighting algorithm for timing-driven placement
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Optimality and scalability study of existing placement algorithms
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Multilevel global placement with congestion control
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient and effective placement for very large circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A study of netlist structure and placement efficiency
Proceedings of the 2004 international symposium on Physical design
Constructive benchmarking for placement
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Large-scale placement by grid-warping
Proceedings of the 41st annual Design Automation Conference
Pre-layout wire length and congestion estimation
Proceedings of the 41st annual Design Automation Conference
Large-Scale Circuit Placement: Gap and Promise
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
An Improved Multi-Level Framework for Force-Directed Placement
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Wire length prediction-based technology mapping and fanout optimization
Proceedings of the 2005 international symposium on Physical design
Multilevel generalized force-directed method for circuit placement
Proceedings of the 2005 international symposium on Physical design
mPL6: a robust multilevel mixed-size placement engine
Proceedings of the 2005 international symposium on Physical design
A congestion-driven placement framework with local congestion prediction
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Timing-driven placement by grid-warping
Proceedings of the 42nd annual Design Automation Conference
Pre-layout Physical Connectivity Prediction with Application in Clustering-Based Placement
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Routability-driven placement and white space allocation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Multilevel expansion-based VLSI placement with blockages
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Optimality study of logic synthesis for LUT-based FPGAs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Floorplan management: incremental placement for gate sizing and buffer insertion
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Solving hard instances of floorplacement
Proceedings of the 2006 international symposium on Physical design
mPL6: enhanced multilevel mixed-size placement
Proceedings of the 2006 international symposium on Physical design
Integrated placement and skew optimization for rotary clocking
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Design and verification of high-speed VLSI physical design
Journal of Computer Science and Technology
Mixed-size placement with fixed macrocells using grid-warping
Proceedings of the 2007 international symposium on Physical design
Integrated placement and skew optimization for rotary clocking
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Solving modern mixed-size placement instances
Integration, the VLSI Journal
A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Artificial bee colony for the standard cell placement problem
International Journal of Metaheuristics
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This paper presents several important enhancements to therecently published multilevel placement package mPL.The improvements include (i) unconstrained quadratic relaxation on small, noncontiguous subproblems at every level of the hierarchy; (ii) improved interpolation (declustering)based on techniques from algebraic multigrid (AMG), and(iii) iterated V-cycles with additional geometric informationfor aggregation in subsequent V-cycles. The enhanced version of mPL, named mPL2, improves the total wirelength result by about 12% compared to the original version. The attractive scalability properties of the mPL run time have beenlargely retained, and the overall run time remains very competitive. Compared to gordian-l-domino on uniform-cell-size IBM/ISPD98 benchmarks, a speed-up of well over8x on large circuits (驴 100,000 cells or nets) is obtainedalong with an average improvement in total wirelength ofabout 2%. Compared to Dragon [32] on the same benchmarks, a speed-up of about 5x is obtained at the cost ofabout 4% increased wirelength. On the recently publishedPEKO synthetic benchmarks, mPL2 generates surprisinglyhigh-quality placements - roughly 60% closer to the optimal than those produced by Capo 8.5 and Dragon - inrun time about twice as long as Capo's and about 1/10th of Dragon's.