Timing driven placement in interaction with netlist transformations
Proceedings of the 1997 international symposium on Physical design
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Physical synthesis methodology for high performance microprocessors
Proceedings of the 40th annual Design Automation Conference
Recursive bisection based mixed block placement
Proceedings of the 2004 international symposium on Physical design
Probabilistic congestion prediction
Proceedings of the 2004 international symposium on Physical design
Efficient timing closure without timing driven placement and routing
Proceedings of the 41st annual Design Automation Conference
Large-scale placement by grid-warping
Proceedings of the 41st annual Design Automation Conference
Modeling repeaters explicitly within analytical placement
Proceedings of the 41st annual Design Automation Conference
An Enhanced Multilevel Algorithm for Circuit Placement
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Routability-driven placement and white space allocation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Optimality and scalability study of existing placement algorithms
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Simultaneous gate sizing and placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal partitioners and end-case placers for standard-cell layout
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Routability-driven white space allocation for fixed-die standard-cell placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Repeater scaling and its impact on CAD
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Recursive bisection placement: feng shui 5.0 implementation details
Proceedings of the 2005 international symposium on Physical design
Optimizing non-monotonic interconnect using functional simulation and logic restructuring
Proceedings of the 2008 international symposium on Physical design
SafeResynth: A new technique for physical synthesis
Integration, the VLSI Journal
Incremental buffer insertion and module resizing algorithm using geometric programming
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
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Incremental physical design is an important methodology towards achieving design closure for high-performance large-scale circuits. Placement tools must accommodate incremental changes to the layout and netlist due to physical synthesis techniques without perturbing the original metrics. We present an incremental placement approach using floorplan sizing to manage the resources and demands of the whole chip region in order to accommodate the changes due to gate sizing and buffer insertion. The experimental results show that this approach can accommodate a wide range of incremental changes without a loss in wirelength and routability. Most important, it also maintains the stability of a placement such that the convergence of physical synthesis iterations can be greatly enhanced.