Incremental buffer insertion and module resizing algorithm using geometric programming

Authors:
Qing Dong;Bo Yang;Jing Li;Shigetoshi Nakatake
Affiliations:
University of Kitakyushu, Kitakyushu, Japan;University of Kitakyushu, Kitakyushu, Japan;University of Kitakyushu, Kitakyushu, Japan;University of Kitakyushu, Kitakyushu, Japan
Venue:
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Year:
2009

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Abstract

This paper presents an efficient algorithm for incremental buffer insertion and module resizing for a full-placed floorplan. Our algorithm offers a method to use the white space in a given floorplan to resize modules and insert buffers, and at the same time keep the resultant floorplan as close to the original one as possible. Both the buffer insertion and module resizing are modelled as geometric programming problems, and can be solved extremely efficiently using new developed solution methods. The experimental results suggest that the the wirelength difference between the initial floorplan and result is quite small (less than 5%), and the global structure of the initial floorplan is preserved very well.