ISPD '00 Proceedings of the 2000 international symposium on Physical design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Floorplanning of pipelined array modules using sequence pairs
Proceedings of the 2003 international symposium on Physical design
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Stable Multiway Circuit Partitioning for ECO
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A novel thermal optimization flow using incremental floorplanning for 3D ICs
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Incremental buffer insertion and module resizing algorithm using geometric programming
Proceedings of the 19th ACM Great Lakes symposium on VLSI
A hierarchical approach for incremental floorplan based on genetic algorithms
ICNC'05 Proceedings of the First international conference on Advances in Natural Computation - Volume Part III
Full Length Article: 3D thermal-aware floorplanner using a MILP approximation
Microprocessors & Microsystems
3D thermal-aware floorplanner using a MOEA approximation
Integration, the VLSI Journal
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One of the foremost problems in physical design for deep-submicron circuits is the need for estimates that depend on future decisions. Estimation of area, timing, and coupling are required..We propose a novel floorplanner, with a new wiring metric, which can be updated quickly in small increments. This provides tools with a way to influence the floorplan as they make changes without a large running time penalty. We provide experimental results that show the incremental approach to be generally 5 times faster than full floorplanning while maintaining good estimates.