Optimal orientations of cells in slicing floorplan designs
Information and Control
Simultaneous functional-unit binding and floorplanning
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A new algorithm for minimizing convex functions over convex sets
Mathematical Programming: Series A and B
Sequence-pair based placement method for hard/soft/pre-placed modules
ISPD '98 Proceedings of the 1998 international symposium on Physical design
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
VLSI module placement based on rectangle-packing by the sequence-pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Handling soft modules in general nonslicing floorplan using Lagrangian relaxation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal aspect ratios of building blocks in VLSI
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2004 international symposium on Physical design
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Floorplanning individual pipelined array modules of a larger overall die can yield beneficial results. Critical paths in every pipeline stage of a pipelined design are roughly equivalent after synthesis. The inability of synthesis tools to predict without full placement both wire congestion and the distance traveled by a wire or wires between consecutive registers are the greatest causes of additional delay and area during place and route. This paper will detail a floorplanning methodology for pipelined arrays that is used to regulate wire congestion and the shortest/longest distances travelled by wire(s) between consecutive registers. A new wire length metric for pipelined arrays will be discussed that attempts to measure the distance travelled by wire(s) between registers. A new move set for floorplanning pipelined arrays using sequence pairs will also be introduced that significantly reduces the annealing design space from previous work. These two contributions when used together have produced up to 10% faster clock periods, 12% smaller designs, and 85% less area used to fix hold time violations in a placed and routed 0.18 μm design.