Rectilinear Shortest Paths and Minimum Spanning Trees in the Presence of Rectilinear Obstacles
IEEE Transactions on Computers
Logical effort: designing for speed on the back of an envelope
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
Layout driven technology mapping
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Performance-oriented technology mapping
Performance-oriented technology mapping
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
A delay model for logic synthesis of continuously-sized networks
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
BooleDozer: logic synthesis for ASICs
IBM Journal of Research and Development
New algorithms for gate sizing: a comparative study
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
Gate sizing for constrained delay/power/area optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
ISPD '98 Proceedings of the 1998 international symposium on Physical design
An interactive maze router with hints
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A simultaneous routing tree construction and fanout optimization algorithm
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Interleaving buffer insertion and transistor sizing into a single optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ISPD '99 Proceedings of the 1999 international symposium on Physical design
On the behavior of congestion minimization during placement
ISPD '99 Proceedings of the 1999 international symposium on Physical design
VIA design rule consideration in multi-layer maze routing algorithms
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Simultaneous routing and buffer insertion with restrictions on buffer locations
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
DUNE: a multi-layer gridless routing system with wire planning
ISPD '00 Proceedings of the 2000 international symposium on Physical design
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Multi-center congestion estimation and minimization during placement
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Depth optimal incremental mapping for field programmable gate arrays
Proceedings of the 37th Annual Design Automation Conference
An implicit connection graph maze routing algorithm for ECO routing
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A sequential detailed router for huge grid graphs
Proceedings of the conference on Design, automation and test in Europe
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
On mismatches between incremental optimizers and instance perturbations in physical design tools
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A Timing-Constrained Incremental Routing Algorithm for Symmetrical FPGAs
EDTC '96 Proceedings of the 1996 European conference on Design and Test
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
DAC '84 Proceedings of the 21st Design Automation Conference
DAC '78 Proceedings of the 15th Design Automation Conference
Discrete drive selection for continuous sizing
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Finding obstacle-avoiding shortest paths using implicit connection graphs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Incremental layout placement modification algorithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Logic Synthesis and Verification
Incremental exploration of the combined physical and behavioral design space
Proceedings of the 42nd annual Design Automation Conference
Optimal wire retiming without binary search
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
TAPHS: thermal-aware unified physical-level and high-level synthesis
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Congestion driven incremental placement algorithm for standard cell layout
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Gibbs sampling in power grid analysis
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Clustering for processing rate optimization
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A new efficient retiming algorithm derived by formal manipulation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Incremental component implementation selection: enabling ECO in compositional system synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Perturb+mutate: Semisynthetic circuit generation for incremental placement and routing
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Incremental buffer insertion and module resizing algorithm using geometric programming
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Clustering for processing rate optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On incremental component implementation selection in system synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A hierarchical approach for incremental floorplan based on genetic algorithms
ICNC'05 Proceedings of the First international conference on Advances in Natural Computation - Volume Part III
Intuitive ECO synthesis for high performance circuits
Proceedings of the Conference on Design, Automation and Test in Europe
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Comprehensive study of incremental algorithms and solutions in the context of CAD tool development is an open area of research with a great deal of potential. Incremental algorithms for synthesis and layout are needed when design undergoes local or incremental change. Often these local changes are made to react to local change in the design, correct local errors or to make local improvements in one or more of the design quality metrics. In this paper we outline fundamental problems in incremental logic synthesis and physical design. Preliminary solutions to a subset of these problems will be outlined.