Multilevel circuit partitioning
DAC '97 Proceedings of the 34th annual Design Automation Conference
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Fast floorplanning for effective prediction and construction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
An orthogonal simulated annealing algorithm for large floorplanning problems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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With more and more interactions between high-level and physical-level design, incremental floorplan is becoming a must to deal with such complexity. In this paper, we propose a hierarchical approach for incremental floorplan based on genetic algorithms. It combines the power of genetic optimization and partition algorithms to provide smooth controllable quality/runtime tradeoffs. Experiments show that our hierarchy approach can provide magnitudes of speedup compared to traditional flatten floorplan using genetic algorithms without much area overhead. Furthermore, incremental change is also supported in such a hierarchical floorplanner, which makes it very promising to be used in the high-level analysis and synthesis environment.