ISPD '00 Proceedings of the 2000 international symposium on Physical design
Noise-aware power optimization for on-chip interconnect
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Built-in self-test for signal integrity
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Signal Integrity: Fault Modeling and Testing in High-Speed SoCs
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Testing Interconnects for Noise and Skew in Gigahertz SoCs
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Digital Circuit Optimization via Geometric Programming
Operations Research
Wire sizing and spacing for lithographic printability and timing optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A class of problems for which cyclic relaxation converges linearly
Computational Optimization and Applications
Proceedings of the 2009 international symposium on Physical design
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In this paper we formulate three classes of optimization problems: the simple, monotonically constrained, and bounded Cong-He (CH)-programs. We reveal the dominance property under the local refinement (LR) operation for the simple CH-program, as well as the general dominance property under the pseudo-LR operation for the monotonically constrained CH-program and the extended-LR operation for the bounded CH-program. These properties enable a very efficient polynomial-time algorithm, using different types of LR operations to compute tight lower and upper bounds of the exact solution to any CH-program. We show that the algorithm is capable of solving many layout optimization problems in deep submicron iterative circuit and/or high-performance multichip module (MCM) and printed circuit board (PCB) designs. In particular, we apply the algorithm to the simultaneous transistor and interconnect sizing problem, and to the global interconnect sizing and spacing problem considering the coupling capacitance for multiple nets. We use tables precomputed from SPICE simulations and numerical capacitance extractions to model device delay and interconnect capacitance, so that our device and interconnect models are much more accurate than many used in previous interconnect optimization algorithms. Experiments show that the bound-computation algorithm can efficiently handle such complex models, and obtain solutions close to the global optimum in most cases. We believe that the CH-program formulations and the bound-computation algorithm can also be applied to other optimization problems in the computer-aided design field