Dominating sets for split and bipartite graphs
Information Processing Letters
New performance-driven FPGA routing algorithms
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Timing-constrained layout algorithms for symmetrical field-programmable gate arrays
Timing-constrained layout algorithms for symmetrical field-programmable gate arrays
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Implementing fine grain processor arrays on field-programmable logic
Integrated Computer-Aided Engineering
On pioneering nanometer-era routing problems
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
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In this paper we present a timing-constrained routing algorithm for symmetrical FPGAs which embodies a novel incremental routing strategy that combines global and detailed routing, and a routing resource allocation algorithm that takes into account both the characteristics of the routing resources and timing information. Experimental results confirm that the algorithm reduces delay along the longest path in the circuit, uses routing resources efficiently, and requires low CPU time.