General models and algorithms for over-the-cell routing in standard cell design
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Minimum crosstalk switchbox routing
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Techniques for crosstalk avoidance in the physical design of high-performance digital systems
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Routing in a new 2-dimensional FPGA/FPIC routing architecture
DAC '94 Proceedings of the 31st annual Design Automation Conference
Routing for symmetric FPGAs and FPICs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Minimum crosstalk channel routing
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A spacing algorithm for performance enhancement and cross-talk reduction
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Global routing with crosstalk constraints
DAC '98 Proceedings of the 35th annual Design Automation Conference
Timing and crosstalk driven area routing
DAC '98 Proceedings of the 35th annual Design Automation Conference
A performance-driven layer assignment algorithm for multiple interconnect trees
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Noise-aware power optimization for on-chip interconnect
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
A Timing-Constrained Incremental Routing Algorithm for Symmetrical FPGAs
EDTC '96 Proceedings of the 1996 European conference on Design and Test
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '76 Proceedings of the 13th Design Automation Conference
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
Crosstalk-Constrained Performance Optimization by Using Wire Sizing and Perturbation
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
On the k-layer planar subset and via minimization problems
EURO-DAC '90 Proceedings of the conference on European design automation
Post global routing crosstalk synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A postprocessing algorithm for crosstalk-driven wire perturbation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On integrating power and signal routing for shield count minimization in congested regions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal wiresizing under Elmore delay model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we present a tribute to Professor C. L. (David) Liu for his numerous contributions in the field of the physical design of VLSI circuits by highlighting some of his work in the area of routing in general, and performance-driven routing in particular. We point out how he pioneered several important problem formulations along with elegant algorithmic solutions for them, often 5-10 years ahead of the time when they would become important in the semiconductor industry. More specifically, we present a brief discussion of his work on the problems of interconnect crosstalk optimization and performance-driven layer assignment, showing how it influenced subsequent academic research as well as the evolution of industrial layout tools, as an illustration of his visionary and transformative approach to physical design.