Constrained via minimization with practical considerations for multi-layer VLSI/PCB routing problems
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
An efficient approach to multi-layer layer assignment with application to via minimization
DAC '97 Proceedings of the 34th annual Design Automation Conference
DAC '78 Proceedings of the 15th Design Automation Conference
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
The retiming and routing of VLSI circuits
The retiming and routing of VLSI circuits
Signal Delay in RC Tree Networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal wiresizing under Elmore delay model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On pioneering nanometer-era routing problems
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
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