Optimal layer assignment for interconnect
Advances in VLSI and Computer Systems
Via minimization for gridless layouts
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Layer Assignment Problem for Three-Layer Routing
IEEE Transactions on Computers
The Via Minimization Problem is NP-Complete
IEEE Transactions on Computers
Constrained via minimization with practical considerations for multi-layer VLSI/PCB routing problems
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Optimal wiresizing for interconnects with multiple sources
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Fast algorithm for optimal layer assignment
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
DAC '76 Proceedings of the 13th Design Automation Conference
An efficient multilayer MCM router based on four-via routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A performance-driven layer assignment algorithm for multiple interconnect trees
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A graph-partitioning-based approach for multi-layer constrained via minimization
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Using grey relation analysis and TOPSIS to measure PCB manufacturing firms efficiency in Taiwan
ISNN'11 Proceedings of the 8th international conference on Advances in neural networks - Volume Part III
| Hi-index | 0.00 |
In this paper, we present an efficient heuristic algorithmfor the layer assignment and via minimization problem formulti-layer gridless IC, PCB, and MCM layout.We introducethe notion of the extended conflict-continuation (ECC)graph to represent the multi-layer layer assignment problem.Our algorithm is based on a linear time optimal algorithmthat solves a special case of the layer assignment problemwhen the ECC graph is a tree.For the general layer assignmentconstructs a sequence of induced subtrees in theECC graph and applies our linear time optimal algorithmto each of the induced subtrees.We have applied this algorithmto the via minimization problem and get very encouragingresults.We have achieved 13%-16% via reduction onthe routing layout generated by V4R router, which is arouter known to have low usage of vias.We successfully appliedour algorithm to routing examples of over 30,000 wiresegments and over 40,000 vias.