Optimal layer assignment for interconnect
Advances in VLSI and Computer Systems
Planar multicommodity flows, maximum matchings and negative cycles
SIAM Journal on Computing
Via minimization for gridless layouts
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Journal of the ACM (JACM)
Graph Algorithms
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
An optimum layer assignment for routing in ICs and PCBs.
DAC '81 Proceedings of the 18th Design Automation Conference
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
SFCS '82 Proceedings of the 23rd Annual Symposium on Foundations of Computer Science
VIA minimization by layout modification
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Constrained via minimization with practical considerations for multi-layer VLSI/PCB routing problems
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
An efficient approach to multi-layer layer assignment with application to via minimization
DAC '97 Proceedings of the 34th annual Design Automation Conference
Track assignment: a desirable intermediate step between global routing and detailed routing
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Conjugate conflict continuation graphs for multi-layer constrained via minimization
Information Sciences: an International Journal
Proceedings of the 2008 international symposium on Physical design
Partitioning planar graphs: a fast combinatorial approach for max-cut
Computational Optimization and Applications
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Given the geometry of wires for interconnections, we want to assign two conducting layers to the segments of these wires so that the number of vias required is minimized. This layer assignment problem, also referred to as the via minimization problem, has been formulated as finding a maximum cut of a planar graph. In this paper, we propose a new algorithm for optimal layer assignment under a general model where the planar graph has real-valued edge weights. The time complexity of the proposed algorithm is O(n3/2 log n) where n is the number of wire-segment clusters in a given layout. In contrast, all existing optimal algorithms for layer assignment have the time complexity of O(n3).