VIA minimization by layout modification
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
The Via Minimization Problem is NP-Complete
IEEE Transactions on Computers
An efficient approach to multi-layer layer assignment with application to via minimization
DAC '97 Proceedings of the 34th annual Design Automation Conference
Fast algorithm for optimal layer assignment
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
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This paper describes a graph theoretic algorithm which, given a particular layout, finds a layer assignment that requires the minimum number of vias. The time complexity of the algorithm is &Ogr;(n3) where n is the number of routing segments in the given layout. Unlike previous algorithms, this algorithm does not require the layout to be grid based and places no constraints on the location of vias or the number of wires that may be joined at a single junction. The algorithm yields globally optimum results when the maximum junction degree is limited to three and has been fully implemented.