FORTRAN Codes for Mathematical Programming: Linear, Quadratic and Discrete
FORTRAN Codes for Mathematical Programming: Linear, Quadratic and Discrete
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
Layer Assignment Problem for Three-Layer Routing
IEEE Transactions on Computers
The Via Minimization Problem is NP-Complete
IEEE Transactions on Computers
Constrained via minimization with practical considerations for multi-layer VLSI/PCB routing problems
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Fast algorithm for optimal layer assignment
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
The constrained via minimization problem for PCB and VLSI design
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A graph-partitioning-based approach for multi-layer constrained via minimization
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A preprocessor for the via minimization problem
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
An analytical method for compacting routing area in integrated circuits
DAC '82 Proceedings of the 19th Design Automation Conference
BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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An optimum layer assignment of interconnections in IC and two-layer PCB is derived. The assignment is optimal in the sense that it is achieved through a global minimization of contacts or vias. The problem is formulated as a 0,1 integer program and solved using a branch and bound technique. There are no constraints on contact location or on the number of wires that can be connected at each contact. Applications of this procedure to VLSI circuits are discussed.