The constrained via minimization problem for PCB and VLSI design

Authors:
Xiao-Ming Xiong;Ernest S. Kuh
Affiliations:
Bell Laboratories, 101 Crawfords Corner Rd., Holmdel, NJ;Bell Laboratories, 101 Crawfords Corner Rd., Holmdel, NJ
Venue:
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Year:
1988

Citing 4
Cited 2

Plane-sweep algorithms for intersecting geometric figures

Communications of the ACM
Computers and Intractability: A Guide to the Theory of NP-Completeness

Computers and Intractability: A Guide to the Theory of NP-Completeness
An optimum layer assignment for routing in ICs and PCBs.

DAC '81 Proceedings of the 18th Design Automation Conference
Wire routing by optimizing channel assignment within large apertures

DAC '71 Proceedings of the 8th Design Automation Workshop

Layout optimization by pattern modification

DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Constrained via minimization with practical considerations for multi-layer VLSI/PCB routing problems

DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference

Quantified Score

Hi-index	0.00

Visualization

Abstract

A new via minimization approach is presented for two layer routing of printed circuit boards and VLSI chips. We have analyzed and characterized different aspects of the problem and have derived an equivalent graph model for the problem from the linear programming formulation. Based on the analysis of our unified formulation, we posed a practical heuristic algorithm. The algorithm can handle both grid-based and gridless routing. Also, an arbitrary number of wires is allowed to intersect at a via and we allow both Manhattan and knock-knee routings.