Geometrical compaction in one dimension for channel routing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
On global wire ordering for macro-cell routing
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
VIA minimization by layout modification
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
The constrained via minimization problem for PCB and VLSI design
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Introduction To Automata Theory, Languages, And Computation
Introduction To Automata Theory, Languages, And Computation
Verification and optimization for LSI & PCB layout
DAC '81 Proceedings of the 18th Design Automation Conference
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This paper introduces a new and practical approach to several layout optimization problems. A novel two-dimensional pattern generator, in connection with a set of routing and placement transformations, is employed to efficiently solve problems ranging from Wire Crossing Minimization and Topological Via Minimization to Minimum Steiner Tree Optimization and IO Alignment. The expected running time is O(nlogn) and the space requirement is O(n), where n is the number of layout objects. The system is fully coded and tested, and excellent results in both laboratory and real-life examples have been achieved.