Layout optimization by pattern modification
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Object oriented Lisp implementation of the CHEOPS VLSI floor planning and routing system
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Chip assembly in the PLAYOUT VLSI design system
EURO-DAC '92 Proceedings of the conference on European design automation
EURO-DAC '92 Proceedings of the conference on European design automation
A new generalized row-based global router
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
On the crossing distribution problem
ACM Transactions on Design Automation of Electronic Systems (TODAES)
EMC-driven midway routing on PCBs
EDTC '95 Proceedings of the 1995 European conference on Design and Test
A hybrid hierarchical approach for multi-layer global routing
EDTC '95 Proceedings of the 1995 European conference on Design and Test
EURO-DAC '90 Proceedings of the conference on European design automation
An ILP for the metro-line crossing problem
CATS '08 Proceedings of the fourteenth symposium on Computing: the Australasian theory - Volume 77
An efficient macro-cell placement algorithm
Integration, the VLSI Journal
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In an automatic routing system for macro-cell layout the wiring area is decomposed into a number of smaller regions. These regions are routed separately by a detailed router such as a channel router or a switch-box router. The position of the pins at the junction between two adjacent regions is usually determined by the detailed router. The locality of this 'bottom-up' ordering disregards the global topologies of the nets which usually span several routing regions. This may result in twisted wires, unnecessary vias and waste of area. An algorithm to prevent twisted wires during detailed routing is presented. A consistent order is determined for the junction pins which ensures that no unnecessary wire twisting is introduced. If wires have to cross their intersection will preferably be placed in such a position that the chip area is least affected.