Algorithms for routing and testing routability of planar VLSI layouts
STOC '85 Proceedings of the seventeenth annual ACM symposium on Theory of computing
Minimum-Area Wiring for Slicing Structures
IEEE Transactions on Computers
On global wire ordering for macro-cell routing
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Combinatorial algorithms for integrated circuit layout
Combinatorial algorithms for integrated circuit layout
Planar subset of multi-terminal nets
Integration, the VLSI Journal
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Phenomena of electromagnetic compatibility (EMC) have to be considered during layout synthesis of printed-circuit boards (PCBs), in order to design failsafe and high-performance systems. In this paper the PCB routing-system HERO, presented in a previous publication, is extended by a new layer-assignment/net-ordering phase, called midway routing, performed after global and before detailed routing. The new method yields a significantly increased completion rate, improved EMC-behavior, and fewer layer changes (vias) in about half the time of the previous version of HERO.