Optimal orientations of cells in slicing floorplan designs
Information and Control
DAC '82 Proceedings of the 19th Design Automation Conference
Canonical embedding of rectangular duals with applications to VLSI floorplanning
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Monotone bipartitioning problem in a planar point set with applications to VLSI
ACM Transactions on Design Automation of Electronic Systems (TODAES)
EMC-driven midway routing on PCBs
EDTC '95 Proceedings of the 1995 European conference on Design and Test
| Hi-index | 14.99 |
In this paper we consider the problem of optimal wiring of VLSI circuits. The topological placement of the circuit elements (macros) on the chip is assumed to have a special hierarchical structure, i.e., to be a slicing floorplan, represented by a binary (slicing) tree. Instead of the usual objective of minimum wire length, we consider the problem of minimizing the overall area of the wired floorplan. For the case of a single multiterminal net connecting n macros, we obtain a wiring algorithm of complexity O(nd), where d is the depth of the slicing tree. The case of several multiterminal nets is still under investigation.