Optimal wiring between rectangles
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
Advances in homotopic layout compaction
SPAA '89 Proceedings of the first annual ACM symposium on Parallel algorithms and architectures
On continuous Homotopic one layer routing
SCG '88 Proceedings of the fourth annual symposium on Computational geometry
Topological routing in SURF: Generating a rubber-band sketch
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Routability of a rubber-band sketch
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Two Steiner tree packing problems
STOC '95 Proceedings of the twenty-seventh annual ACM symposium on Theory of computing
Node-disjoint paths on the mesh and a new trade-off in VLSI layout
STOC '96 Proceedings of the twenty-eighth annual ACM symposium on Theory of computing
Recent results in VLSI CAD at MIT
ACM '86 Proceedings of 1986 ACM Fall joint computer conference
TEG: a new post-layout optimization method
Proceedings of the 2002 international symposium on Physical design
Proceedings of the eighteenth annual symposium on Computational geometry
SURF: Rubber-Band Routing System for Multichip Modules
IEEE Design & Test
Research directions for coevolution of rules and routers
Proceedings of the 2003 international symposium on Physical design
Computing homotopic shortest paths in the plane
SODA '03 Proceedings of the fourteenth annual ACM-SIAM symposium on Discrete algorithms
Computing Homotopic Shortest Paths Efficiently
ESA '02 Proceedings of the 10th Annual European Symposium on Algorithms
EMC-driven midway routing on PCBs
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Computing homotopic shortest paths in the plane
Journal of Algorithms
The oct-touched tile: a new architecture for shape-based routing
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Computing homotopic shortest paths efficiently
Computational Geometry: Theory and Applications
Thick non-crossing paths and minimum-cost flows in polygonal domains
SCG '07 Proceedings of the twenty-third annual symposium on Computational geometry
A correct network flow model for escape routing
Proceedings of the 46th Annual Design Automation Conference
Computing homotopic shortest paths efficiently
Computational Geometry: Theory and Applications
Planar subset of multi-terminal nets
Integration, the VLSI Journal
A new physical routing approach for robust bundled signaling on NoC links
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Topology-driven cell layout migration with collinear constraints
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Homotopic rectilinear routing with few links and thick edges
LATIN'10 Proceedings of the 9th Latin American conference on Theoretical Informatics
System-in-Package: Electrical and Layout Perspectives
Foundations and Trends in Electronic Design Automation
GD'12 Proceedings of the 20th international conference on Graph Drawing
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This paper studies the problem of routing wires in a grid among features on one layer of a VLSI chip, when a sketch of the layer is given. A sketch specifies the positions of features and the topology of the interconnecting wires. We give polynomial-time algorithms that (1) determine the routability of a sketch, and (2) produce a routing of a sketch that optimizes both individual and total wire length. These algorithms subsume most of the polynomial-time algorithms in the literature for planar routing and routability testing in the rectilinear grid model. We also provide an explicit construction of a database, called the rubber-band equivalent, to support computation involving the layout topology.