Algorithms for routing and testing routability of planar VLSI layouts
STOC '85 Proceedings of the seventeenth annual ACM symposium on Theory of computing
An efficient timing-driven global routing algorithm
DAC '93 Proceedings of the 30th international Design Automation Conference
Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs
Proceedings of the 2002 international symposium on Physical design
Algorithms for VLSI Physcial Design Automation
Algorithms for VLSI Physcial Design Automation
Topological routing of multi-bit data buses
DAC '84 Proceedings of the 21st Design Automation Conference
Optimal shielding/spacing metrics for low power design
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Multi-bend bus driven floorplanning
Proceedings of the 2005 international symposium on Physical design
Buffer insertion under process variations for delay minimization
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
GALS networks on chip: a new solution for asynchronous delay-insensitive links
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Low-power network-on-chip for high-performance SoC design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Semi-detailed bus routing with variation reduction
Proceedings of the 2007 international symposium on Physical design
Enabling Technology for On-Chip Interconnection Networks
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Topology-based optimization of maximal sustainable throughput in a latency-insensitive system
Proceedings of the 44th annual Design Automation Conference
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Variation tolerant NoC design by means of self-calibrating links
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 2nd International Workshop on Network on Chip Architectures
Proceedings of the Conference on Design, Automation and Test in Europe
Error control schemes for on-chip communication links: the energy-reliability tradeoff
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Mesochronous NoC technology for power-efficient GALS MPSoCs
Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip
Proceedings of the 4th International Workshop on Network on Chip Architectures
International Journal of Embedded and Real-Time Communication Systems
A resilient architecture for low latency communication in shared-L1 processor clusters
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Tightly matched signal propagation and strong crosstalk protection are key requirements for next-generation NoC links featuring GALS synchronization and low-swing signaling. In this paper, we present a new methodology for NoC global link routing which addresses these challenges. Our approach creates bundled link routes with geometrically matched wires, thus leading to much reduced intra-link variations. Moreover, our link router supports high-regularity wire spacing and shielding strategies. Delay variation among different wires of a link is 25% to 70% lower than what can be achieved using a state-of-the-art timing-driven global routing flow. Additionally, crosstalk effects are reduced by more than 30%.