An Asynchronous Router for Multiple Service Levels Networks on Chip
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
×pipes Lite: A Synthesis Oriented Design Library For Networks on Chips
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook
IEEE Design & Test
Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Low-Complexity Link Microarchitecture for Mesochronous Communication in Networks-on-Chip
IEEE Transactions on Computers
Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Design perspectives on 22nm CMOS and beyond
Proceedings of the 46th Annual Design Automation Conference
Proceedings of the 2nd International Workshop on Network on Chip Architectures
An Open and Reconfigurable Platform for 4G Telecommunication: Concepts and Application
DSD '09 Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
A new physical routing approach for robust bundled signaling on NoC links
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
A fully-asynchronous low-power framework for GALS NoC integration
Proceedings of the Conference on Design, Automation and Test in Europe
Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs
Proceedings of the Conference on Design, Automation and Test in Europe
Strategic directions towards multicore application specific computing
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the 4th International Workshop on Network on Chip Architectures
Exploring topologies for source-synchronous ring-based network-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
A fast, source-synchronous ring-based network-on-chip design
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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MPSoCs are today frequently designed as the composition of multiple voltage/frequency islands, thus calling for a GALS clocking style. In this context, the on-chip interconnection network can be either inferred as a single and independent clock domain or it can be distributed among core's domains. This paper targets the former scenario, since it results in the homogeneous speed of the NoC switching elements. From a physical design viewpoint, the main issues lie however in the chip-wide extension of the network domain and in the growing uncertainties affecting nanoscale silicon technologies. This paper proves that partitioning the network into mesochronous domains and merging synchronizers with NoC building blocks, two main advantages can be achieved. First, it is possible to evolve synchronous networks to mesochronous ones with marginal performance and area overhead. Second, the mesochronous NoC exposes more degrees of freedom for power optimization.