The turn model for adaptive routing
Journal of the ACM (JACM)
Wormhole routing techniques for directly connected multicomputer systems
ACM Computing Surveys (CSUR)
The Odd-Even Turn Model for Adaptive Routing
IEEE Transactions on Parallel and Distributed Systems
The Impact of Link Arbitration on Switch Performance
HPCA '99 Proceedings of the 5th International Symposium on High Performance Computer Architecture
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Architecture of the Scalable Communications Core
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Wireless innovation through software radios
ACM SIGCOMM Computer Communication Review
A Communication and configuration controller for NoC based reconfigurable data flow architecture
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration
Proceedings of the Conference on Design, Automation and Test in Europe
Adaptive and deadlock-free tree-based multicast routing for networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An analytical network performance model for SIMD processor CSX600 interconnects
Journal of Systems Architecture: the EUROMICRO Journal
Mesochronous NoC technology for power-efficient GALS MPSoCs
Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip
Key lessons from the scalable communications core: a reconfigurable wireless baseband
IEEE Communications Magazine
Microprocessors & Microsystems
DBAR: an efficient routing algorithm to support multiple concurrent applications in networks-on-chip
Proceedings of the 38th annual international symposium on Computer architecture
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The SCC is a flexible and energy- and area-efficient baseband processor for concurrent multiple wireless protocols. Its architecture consists of coarse-grained, heterogeneous, programmable accelerators connected via a packet-based, 3-ary 2-cube network on chip. The NoC supports goals of flexibility, scalability, and extensibility, and it meets stringent latency and throughput requirements.