Architecture of the Scalable Communications Core

Authors:
Jeff Hoffman;David Arditti Ilitzky;Anthony Chun;Aliaksei Chapyzhenka
Affiliations:
Intel Corporation, California, USA;Intel Corporation, California, USA;Intel Corporation, California, USA;Intel Corporation, California, USA
Venue:
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Year:
2007

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Abstract

The Scalable Communications Core (SCC) is a power- and area-efficient solution for physical layer (PHY) and lower MAC processing of concurrent multiple wireless protocols. Our architecture consists of coarse-grained, heterogeneous, programmable accelerators connected via a packet-based 3-ary 2- cube Network on Chip (NoC). The combination of the accelerators, which were developed for key communications operations, and the NoC results in an architecture that is flexible for multiple protocols, extensible for future standards and scalable to support multiple simultaneous streams.