From SODA to scotch: The evolution of a wireless baseband processor
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Overview of the Scalable Communications Core: A Reconfigurable Wireless Baseband in 65nm CMOS
ISVLSI '09 Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI
| Hi-index | 0.25 |
The radios in mobile Internet devices and smart phones need to support a wide range of wireless standards for cellular, broadband, local, and personal area network connectivity, satellite navigation, and broadcast digital television in a small form factor with low energy consumption. The customary approach is to integrate an optimized antenna, front-end, baseband, and MAC for each protocol; however, any upgrades or modifications for new or different product definitions require a costly respin of the silicon. An alternative approach is to integrate flexible components including an antenna, front-end, baseband, and MAC into a radio that enables one set of hardware to satisfy multiple protocols and also provides scalability for protocol changes in the future; however, there is a penalty in terms of area and power that has to be considered. An example of a flexible baseband is the Scalable Communications Core. This core was developed by Intel Labs and consists of a heterogeneous set of coarse-grained programmable accelerators connected via a packet-based network-on-chip. To understand the area and power cost of the architecture, we taped out a prototype SCC test chip in a 65 nm CMOS process, and programmed and validated it for multiple protocols, including WiFi, WiMAX, GPS, Bluetooth, and DVB-H. This article summarizes our key results in architecture, programming, interconnection, and performance of a flexible baseband for realtime wireless communications applications.