On-Chip Interconnection Architecture of the Tile Processor

Authors:
David Wentzlaff;Patrick Griffin;Henry Hoffmann;Liewei Bao;Bruce Edwards;Carl Ramey;Matthew Mattina;Chyi-Chang Miao;John F. Brown III;Anant Agarwal
Affiliations:
Tilera;Tilera;Tilera;Tilera;Tilera;Tilera;Tilera;Tilera;Tilera;Tilera
Venue:
IEEE Micro
Year:
2007

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Abstract

iMesh, the Tile Processor Architecture's on-chip interconnection network, connects the multicore processor's tiles with five 2D mesh networks, each specialized for a different use. Taking advantage of the five networks, the c-based iLib interconnection library efficiently maps program communication across the on-chip interconnect. The Tile Processor's first implementation, the TILE64, contains 64 cores and can execute 192 billion 32-bit operations per second at 1 GHz.