A Group-Theoretic Model for Symmetric Interconnection Networks
IEEE Transactions on Computers
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As the need for data processing and communication increases, and likewise, as the number of processing cores placed on a given single chip increases, improving the performance of interconnection networks is vital. In the present work, traditional topologies are re-examined. Torus is shown to be a good structure in terms of average latency and symmetry. When using torus in combination with high process levels, it is possible to design new, yet asymmetrical topologies that can meet the high communication performance requirements of many-core processors and also suit a large variety of traffic patterns. Firstly, this paper presents two novel and torus-like topologies called xtorus and xxtorus, which are evaluated by using both theoretical analysis and experimental simulation methods. For theoretical analysis, an algorithm for computing link path diversity and link entropy is given. The analysis shows that, compared with mesh, xmesh and torus, the proposed topologies have better properties in terms of diameter, average latency, throughput, and path diversity. Although more links are added, the number of links is of the same order of magnitude with that of mesh, xmesh, and torus. Proposed topologies also take advantage of increasingly higher levels of the VLSI process. Simulations on GEM5 reveal that xtorus has better scalability, and that its average latency is less than that of mesh, xmesh and torus by significant proportions respectively, particularly when the network scale is larger. Moreover, for different traffic patterns, its performance swing is less than that of mesh. Furthermore, in the present work, the proposed topologies are both asymmetrical and based on the entropy difference of the links in the topology. A strategy for heterogeneous link design is presented, which enables designers to trade off between delay, power and area according to a concrete integrated circuit design scene.