Design and formal verification of a hierarchical cache coherence protocol for NoC based multiprocessors

Authors:
Hemangee K. Kapoor;Praveen Kanakala;Malti Verma;Shirshendu Das
Affiliations:
Department of Computer Science and Engineering, Indian Institute of Technology Guwahati, Guwahati, India 781 039;Department of Computer Science and Engineering, Indian Institute of Technology Guwahati, Guwahati, India 781 039;Department of Computer Science and Engineering, Indian Institute of Technology Guwahati, Guwahati, India 781 039;Department of Computer Science and Engineering, Indian Institute of Technology Guwahati, Guwahati, India 781 039
Venue:
The Journal of Supercomputing
Year:
2013

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Abstract

Advancement in semiconductor technology is allowing to pack more and more processing cores on a single die and scalable directory based protocols are needed for maintaining cache coherence. Most of the currently available directory based protocols are designed for mesh based topology and have the problem of delay and scalability. Cluster based coherence protocol is a better option than flat directory based protocol but the problem of mesh based topology is still exits. On the other hand, tree based topology takes fewer hop counts compared to mesh based topology.In this paper we give a hierarchical cache coherence protocol based on tree based topology. We divide the processing cores into clusters and each cluster shares a higher-level cache. At the next level we form clusters of caches connected to yet another higher-level cache. This is continued up to the top level cache/memory. We give various architectural placements that can benefit from the protocol; hop-count comparison; and memory overhead requirements. Finally, we formally verify the protocol using the Mur驴 tool.