A multi-level hierarchical cache coherence protocol for multiprocessors

  • Authors:

  • Anderson; Baer

  • Affiliations:

  • Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA;Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA

  • Venue:
  • IPPS '93 Proceedings of the 1993 Seventh International Parallel Processing Symposium
  • Year:
  • 1993

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Abstract

In order to meet the computational needs of the next decade, shared-memory processors must be scalable. Though single shared-bus architectures have been successful in the past, lack of bus bandwidth restricts the number of processors that can be effectively put on a single bus machine. One architecture that has been proposed to solve the limited bandwidth problem consists of processors connected via a tree hierarchy of buses. The authors present a tool to study a hierarchical bus based shared-memory system. They highlight the main features of a hierarchical cache coherence protocol and give some preliminary performance results obtained via an instruction level simulator.