IEEE Transactions on Parallel and Distributed Systems
Will networks on chip close the productivity gap?
Networks on chip
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
X10: an object-oriented approach to non-uniform cluster computing
OOPSLA '05 Proceedings of the 20th annual ACM SIGPLAN conference on Object-oriented programming, systems, languages, and applications
NoCs Simulation Framework for OMNeT++
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Fast architecture evaluation of heterogeneous MPSoCs by host-compiled simulation
Proceedings of the 15th International Workshop on Software and Compilers for Embedded Systems
A Scalable NoC Router Design Providing QoS Support Using Weighted Round Robin Scheduling
ISPA '12 Proceedings of the 2012 IEEE 10th International Symposium on Parallel and Distributed Processing with Applications
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Multi- and many-core systems become more and more mainstream and therefore new communication infrastructures like Networks-on-Chip (NoC) and new programming languages like IBM's X10 with its partitioned global address space (PGAS) are introduced. In this paper we present an X10-based simulator, which is capable to simulate the network traffic that occurs inside the X10 program. This holistic approach enables to simulate the functionality and the indicated traffic together, in contrast to pure network simulators where usually only synthetic traffic or traces are used. We explain how the communication overhead is extracted from the X10 run-time and how to simulate the NoC behavior. In experiments we show that the proposed simulator is up to 10 x faster than a comparable SystemC-based simulator and at the same time preserves high accuracy. Furthermore, we present a quality and simulation speed tradeoff by using different simulation modes for a set of real world parallel applications.