Fast architecture evaluation of heterogeneous MPSoCs by host-compiled simulation

  • Authors:

  • Sascha Roloff;Frank Hannig;Jürgen Teich

  • Affiliations:

  • University of Erlangen-Nuremberg, Germany;University of Erlangen-Nuremberg, Germany;University of Erlangen-Nuremberg, Germany

  • Venue:
  • Proceedings of the 15th International Workshop on Software and Compilers for Embedded Systems
  • Year:
  • 2012

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Abstract

Many domain-specific MPSoCs are heterogeneous and tiled by nature. For evaluating important architectural decisions such as tile structure and core selection within each tile for future 100--1000 core designs, fast and flexible simulation approaches are mandatory. Thus, cycle-accurate simulation techniques or co-simulation approaches using simulator coupling are improper. In this paper, we evaluate heterogeneous tiled MPSoCs using a timing-approximate simulation approach. This simulation approach takes particularly into account applications with highly dynamic thread and workload distributions and resource-aware program behavior. Here, the application itself may decide which set of resources is claimed in dependence on run-time status information of the resources (e. g., temperature, load). In order to verify performance goals of the heterogeneous MPSoC apart from functional correctness, we propose a timing-approximate simulation approach, which is based on a discrete-event host-compiled simulation and a time-warping mechanism to scale the elapsed execution times on the simulation host to the simulated target. It allows the investigation of phases of thread (re-)distribution and resource-awareness with an appropriate accuracy. For selected case studies, it is shown how architectural parameters may be varied very fast enabling the exploration of different designs for cost, performance, and other design objectives.