EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
DATE '00 Proceedings of the conference on Design, automation and test in Europe
A decade of reconfigurable computing: a visionary retrospective
Proceedings of the conference on Design, automation and test in Europe
Design space characterization for architecture/compiler co-exploration
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
An algorithm for mapping loops onto coarse-grained reconfigurable architectures
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems
PACT XPP—A Self-Reconfigurable Data Processing Architecture
The Journal of Supercomputing
Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Architecture Exploration for a Reconfigurable Architecture Template
IEEE Design & Test
Introduction to Automata Theory, Languages, and Computation (3rd Edition)
Introduction to Automata Theory, Languages, and Computation (3rd Edition)
Processor Description Languages
Processor Description Languages
Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Fast architecture evaluation of heterogeneous MPSoCs by host-compiled simulation
Proceedings of the 15th International Workshop on Software and Compilers for Embedded Systems
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In this paper, we present a new concept for modeling of interconnection networks in the field of massively parallel processor embedded architectures. The main focus of the paper is on two interconnection concepts, namely, interconnect-wrapper and DyRIBox definitions of reconfigurable interconnection networks. We compare both interconnection concepts against each other and formally prove their equality. Both concepts allow to model many different reconfigurable inter-processor networks efficiently. Furthermore, we point out how to define the interconnect using an architecture description language for massively parallel processor architectures called MAML. Finally, we demonstrate the pertinence of our approach by modeling and evaluation of different reconfigurable interconnect topologies.