Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures

Authors:
Dmitrij Kissler;Andreas Strawetz;Frank Hannig;Jürgen Teich
Affiliations:
Hardware/Software Co-Design Department of Computer Science, University of Erlangen-Nuremberg, Germany;Hardware/Software Co-Design Department of Computer Science, University of Erlangen-Nuremberg, Germany;Hardware/Software Co-Design Department of Computer Science, University of Erlangen-Nuremberg, Germany;Hardware/Software Co-Design Department of Computer Science, University of Erlangen-Nuremberg, Germany
Venue:
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Year:
2009

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Abstract

Coarse-grained reconfigurable architectures deliver high performance and energy efficiency for computationally intensive applications like mobile multimedia and wireless communication. This paper deals with the aspect of power-efficient dynamic reconfiguration control techniques in such architectures. Proper clock domain partitioning with custom clock gating combined with automatic clock gating resulted in a 35% total power reduction. This is more than a threefold as compared to the single clock gating techniques applied separately. The corresponding case study application with 0.064 mW/MHz and 124 MOPS/mW power efficiency outperforms the major coarse-grained and general purpose embedded processor architectures by a factor of 1.7 to 28.