NoC simulation in heterogeneous architectures for PGAS programming model
Proceedings of the 16th International Workshop on Software and Compilers for Embedded Systems
Virtual networks -- distributed communication resource management
ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special Section on 19th Reconfigurable Architectures Workshop (RAW 2012)
Providing multiple hard latency and throughput guarantees for packet switching networks on chip
Computers and Electrical Engineering
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Networks on Chip are the most promising approach to cope with communication requirements in future many core SoCs. Depending on the executed applications, communication requirements may vary at run-time. Dynamic reservation of communication resources in virtual channel NoCs is an encouraging approach for connection-oriented communication guaranteeing QoS. This paper presents a concept enhancing virtual channel reservation to support different bandwidth and latency guarantees. The used weighted round robin scheduling provides hard guarantees regarding throughput and latency. The proposed router design enables dynamic sharing of communication resources between connectionless Best Effort and connection-oriented Guaranteed Service traffic. Due to decentralized routing and resource management it offers a very good scalability for future many core architectures. Simulation results are obtained from a 10x10 NoC with a cycle accurate SystemC router model. The presented results are compared to existing round robin arbitration schemes and show the advantage of the proposed concept. Synthesis results expose its low area overhead.