DAC '97 Proceedings of the 34th annual Design Automation Conference
Getting to the bottom of deep submicron
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Reuse methodology manual: for system-on-a-chip designs
Reuse methodology manual: for system-on-a-chip designs
Getting to the bottom of deep submicron II: a global wiring paradigm
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Surviving the SOC revolution: a guide to platform-based design
Surviving the SOC revolution: a guide to platform-based design
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Addressing the system-on-a-chip interconnect woes through communication-based design
Proceedings of the 38th annual Design Automation Conference
Micronetwork-based integration for SOCs: 673
Proceedings of the 38th annual Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Technology for IP Reuse and Portability
IEEE Design & Test
Networks on Silicon: Combining Best-Effort and Guaranteed Services
Proceedings of the conference on Design, automation and test in Europe
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
System-level design: orthogonalization of concerns and platform-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Operating-system controlled network on chip
Proceedings of the 41st annual Design Automation Conference
Run-time support for heterogeneous multitasking on reconfigurable SoCs
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Local search: is brute-force avoidable?
IJCAI'09 Proceedings of the 21st international jont conference on Artifical intelligence
An overview of achieving energy efficiency in on-chip networks
International Journal of Communication Networks and Distributed Systems
NoC simulation in heterogeneous architectures for PGAS programming model
Proceedings of the 16th International Workshop on Software and Compilers for Embedded Systems
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We introduce two properties of the design process called the arbitrary composability and the linear effort properties. We argue that a design paradigm, which has these two properties is scalable and has the potential to keep up with the pace of technology advances. Then we discuss some of the trends that will enforce significant changes on current design methodologies and techniques. Finally, we argue that the emerging Network-on-Chip (NoC) paradigm promises to address these trends and challenges and has all prerequisites to provide the arbitrary composability and the linear effort properties. Consequently we conclude that NoC is a likely basis for future System-on-Chip platforms and methodologies.