Getting to the bottom of deep submicron II: a global wiring paradigm

Power supply design parameters prediction for high performance IC design flows

SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction

Meeting delay constraints in DSM by minimal repeater insertion

DATE '00 Proceedings of the conference on Design, automation and test in Europe

Rethinking Deep-Submicron Circuit Design

Computer

Hierarchical power supply noise evaluation for early power grid design prediction

Proceedings of the 2001 international workshop on System-level interconnect prediction

Boosters for driving long on-chip interconnects: design issues, interconnect synthesis and comparison with repeaters

Proceedings of the 2001 international symposium on Physical design

Future performance challenges in nanometer design

Proceedings of the 38th annual Design Automation Conference

The future of logic synthesis and verification

Logic Synthesis and Verification

Power Supply Design Parameters for Switching-Noise Control in Deep-Submicron Circuits Design Flows

Analog Integrated Circuits and Signal Processing

Power-Driven Challenges in Nanometer Design

IEEE Design & Test

The scaling challenge: can correct-by-construction design help?

Proceedings of the 2003 international symposium on Physical design

Repeater and current-sensing hybrid circuits for on-chip interconnects

Proceedings of the 13th ACM Great Lakes symposium on VLSI

Will networks on chip close the productivity gap?

Networks on chip

Maximizing throughput over parallel wire structures in the deep submicrometer regime

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

TLC: Transmission Line Caches

Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture

NoCIC: a spice-based interconnect planning tool emphasizing aggressive on-chip interconnect circuit methods

Proceedings of the 2004 international workshop on System level interconnect prediction

Mitigating static power in current-sensed interconnects

Proceedings of the 14th ACM Great Lakes symposium on VLSI

Approaches to run-time and standby mode leakage reduction in global buses

Proceedings of the 2004 international symposium on Low power electronics and design

Adaptive supply voltage technique for low swing interconnects

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

Managing Wire Delay in Large Chip-Multiprocessor Caches

Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture

DVS for On-Chip Bus Designs Based on Timing Error Correction

Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design

Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design

The scaling of interconnect buffer needs

Proceedings of the 2006 international workshop on System-level interconnect prediction

An energy-efficient temporal encoding circuit technique for on-chip high performance buses

GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI

Global signaling over lossy transmission lines

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

Self-timed regenerators for high-speed and low-power on-chip global interconnect

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

On the decreasing significance of large standard cells in technology mapping

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design

Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip

Proceedings of the 19th ACM Great Lakes symposium on VLSI

Bus energy consumption for multilevel signals

IEEE Transactions on Circuits and Systems Part I: Regular Papers

Dynamically pulsed MTCMOS with bus encoding for reduction of total power and crosstalk noise

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints

Proceedings of the Conference on Design, Automation and Test in Europe

Effectiveness of adaptive supply voltage and body bias as post-silicon variability compensation techniques for full-swing and low-swing on-chip communication channels

Proceedings of the Conference on Design, Automation and Test in Europe

Differential current-sensing for on-chip interconnects

IEEE Transactions on Very Large Scale Integration (VLSI) Systems