Getting to the bottom of deep submicron II: a global wiring paradigm
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Interconnect estimation and planning for deep submicron designs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
| Hi-index | 0.00 |
Trends in CMOS technology and VLSI architectures are causing interconnect to play an increasing role in overall performance, power consumption and design effort. Traditionally, repeaters are used for driving long on-chip interconnects, however recent studies indicate that repeaters are using increasing area, power, and design resources as well as having an inherent limit in how much they can improve performance [4,10,14]. This paper presents a new circuit called a {\bf booster} which compares favorably with repeaters in terms of area, performance, power and placement sensitivity. Boosters also have the advantage of being bidirectional and providing a low impedance termination to improve signal integrity. Driver edge rates are slower and peak power is drastically reduced compared to repeaters, thus improving signal integrity and mitigating inductive effects. Boosters are shown to be more than 20\% faster for driving a variety of interconnect loads over conventional repeaters in 0.16 $\mu$m CMOS technology. Boosters are typically inserted three times less frequently than repeaters for optimal performance, resulting in fewer boosters for driving the same interconnect lengths thereby saving on area, power and placement effort.Unlike differential, dynamic or low-swing techniques which require significantly more sophisticated circuit design and hence are cumbersome for automatic interconnect synthesis tools, boosters can be inserted on lines in a straightforward manner. Based on analytical delay models, we derive rules for insertion and sizing of boosters that can easily be incorporated into a CAD tool. We formulate two design rules that determine 1) the number of boosters needed, 2) their placements and 3) sizes, for driving a given interconnect load, first minimizing delay, and then area and power. Power analysis is slightly more complex than for repeaters so we present a systematic design approach. A placement sensitivity analysis comparing