Formal hardware verification by symbolic ternary trajectory evaluation
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Algorithms for approximate FSM traversal
DAC '93 Proceedings of the 30th international Design Automation Conference
Zero-suppressed BDDs for set manipulation in combinatorial problems
DAC '93 Proceedings of the 30th international Design Automation Conference
Noise strategies for improving local search
AAAI '94 Proceedings of the twelfth national conference on Artificial intelligence (vol. 1)
Sequential synthesis using S1S
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A new method to express functional permissibilities for LUT based FPGAs and its applications
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Algebraic decision diagrams and their applications
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
The maximum set of permissible behaviors for FSM networks
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Sequential optimisation without state space exploration
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
DAC '98 Proceedings of the 35th annual Design Automation Conference
Approximate reachability with BDDs using overlapping projections
DAC '98 Proceedings of the 35th annual Design Automation Conference
Making complex timing relationships readable: Presburger formula simplicication using don't cares
DAC '98 Proceedings of the 35th annual Design Automation Conference
Wireplanning in logic synthesis
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Implementation and use of SPFDs in optimizing Boolean networks
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Getting to the bottom of deep submicron
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
Getting to the bottom of deep submicron II: a global wiring paradigm
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A novel VLSI layout fabric for deep sub-micron applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
An Approach to Multilevel Boolean Minimization
Journal of the ACM (JACM)
Technology mapping for k/m-macrocell based FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Wireless protocols design: challenges and opportunities
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Performance driven multi-level and multiway partitioning with retiming
Proceedings of the 37th Annual Design Automation Conference
Circuit design challenges beyond 0.18 micron
ICCAD '00 Proceedings of the 2000 international conference on Computer-aided design
Logic optimization and code generation for embedded control applications
Proceedings of the ninth international symposium on Hardware/software codesign
Circuit-based Boolean Reasoning
Proceedings of the 38th annual Design Automation Conference
Using symbolic algebra in algorithmic level DSP synthesis
Proceedings of the 38th annual Design Automation Conference
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
SAT-Based Image Computation with Application in Reachability Analysis
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Mona: Monadic Second-Order Logic in Practice
TACAS '95 Proceedings of the First International Workshop on Tools and Algorithms for Construction and Analysis of Systems
A Comparison of Presburger Engines for EFSM Reachability
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
A Multilevel-Cell 32Mb Flash Memory
ISMVL '00 Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic
Layout aware synthesis
Introduction to generalized symbolic trajectory evaluation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Efficient retiming of large circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Self-referential verification of gate-level implementations of arithmetic circuits
Proceedings of the 39th annual Design Automation Conference
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Logic synthesis has been worked on for at least 40 years, and much has been accomplished, with many commercial tools developed and used pervasively. However, in light of the continual progress made in technology, more complex designs will be made and along with increased physical interactions, these will present new changes for both synthesis and verification. We discuss some areas where these problems will arise and pose some challenges for the future.