Sequential synthesis using S1S

Authors:
Adnan Aziz;Felice Balarin;Robert Brayton;Alberto Sangiovanni-Vincentelli
Affiliations:
Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA;Cadence Design Systems, Cadence Berkeley Laboratories, Berkeley, CA;Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA;Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA
Venue:
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Year:
1995

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Abstract

We present a mathematical framework for analyzing the synthesis of interacting finite state systems. The logic S1S is used to derive simple, rigorous, and constructive solutions to problems in sequential synthesis. We obtain exact and approximate sets of permissible FSM network behavior, and address the issue of FSM realizability. This approach is also applied to synthesizing systems with fairness and timed systems.