Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
Incremental Synthesis for Engineering Changes
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Sequential synthesis using S1S
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Optimizing designs containing black boxes
DAC '97 Proceedings of the 34th annual Design Automation Conference
Convertibility verification and converter synthesis: two faces of the same coin
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Modeling and optimization of hierarchical synchronous circuits
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Constructive Analysis of Cyclic Circuits
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Pattern-based verification of connections to intellectual property cores
Integration, the VLSI Journal
Constructive Boolean circuits and the exactness of timed ternary simulation
Formal Methods in System Design
Synchronous digital circuits as functional programs
ACM Computing Surveys (CSUR)
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