System clock estimation based on clock slack minimization
EURO-DAC '92 Proceedings of the conference on European design automation
Sequential synthesis using S1S
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Clock-driven performance optimization in interactive behavioral synthesis
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
Fast Prototyping of Datapath-Intensive Architectures
IEEE Design & Test
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Performance optimization using template mapping for datapath-intensive high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Improved force-directed scheduling in high-throughput digital signal processing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-level synthesis under multi-cycle interconnect delay
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Timing variation-aware scheduling and resource binding in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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