Fast and extensive system-level memory exploration for ATM applications
ISSS '97 Proceedings of the 10th international symposium on System synthesis
A Systolic Design Methodology with Application toFull-Search Block-Matching Architectures
Journal of VLSI Signal Processing Systems
Time constrained modulo scheduling with global resource sharing
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Performance-driven scheduling with bit-level chaining
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Parallel Algorithms for Force Directed Scheduling of Flattened and Hierarchical Signal Flow Graphs
IEEE Transactions on Computers
Interactive co-design of high throughput embedded multimedia
Proceedings of the 37th Annual Design Automation Conference
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Data and memory optimization techniques for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low power storage cycle budget distribution tool support for hierarchical graphs
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Data Memory Organization and Optimizations in Application-Specific Systems
IEEE Design & Test
HiPC '00 Proceedings of the 7th International Conference on High Performance Computing
Multidimensional periodic scheduling: a solution approach
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Flow Graph Balancing for Minimizing the Required Memory Bandwidth
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Gradual Relaxation Techniques with Applications to Behavioral Synthesis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A unified approach for scheduling and allocation
Integration, the VLSI Journal
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This paper discusses improved force-directed scheduling and its application in the design of high-throughput DSP systems, such as real-time video VLSL circuits. We present a mathematical justification of the technique of force-directed scheduling, introduced by Paulin and Knight (1989), and we show how the algorithm can be used to find cost-effective time assignments and resource allocations, allowing trade-offs between processing units and memories. Furthermore, we present modifications that improve the effectiveness and the efficiency of the algorithm. The significance of the improvements is illustrated by an empirical performance analysis based on a number of problem instances