Parallel test generation for sequential circuits on general-purpose multiprocessors
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Sequential circuit test generation on a distributed system
DAC '93 Proceedings of the 30th international Design Automation Conference
Parallel algorithms for VLSI computer-aided design
Parallel algorithms for VLSI computer-aided design
Using MPI: portable parallel programming with the message-passing interface
Using MPI: portable parallel programming with the message-passing interface
Improved algorithms for high-level synthesis and their parallel implementations
Improved algorithms for high-level synthesis and their parallel implementations
DSS: A Distributed High-Level Synthesis System
IEEE Design & Test
Parallel Algorithms for Force Directed Scheduling of Flattened and Hierarchical Signal Flow Graphs
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Parallel algorithms for logic synthesis using the MIS approach
IPPS '95 Proceedings of the 9th International Symposium on Parallel Processing
Improved force-directed scheduling in high-throughput digital signal processing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 14.98 |
In this paper, we present some novel algorithms for scheduling hierarchical signal flow graphs in the domain of high-level synthesis. With complex chips that need to be designed in the future, it is expected that the runtimes of these scheduling algorithms will be quite large. The key contributions of this paper are as follows: First, we develop a novel extension of the sequential force-directed scheduling algorithm which naturally handles loops and conditionals by coming up with a scheme of scheduling hierarchical signal flow graphs. Second, we develop three new parallel algorithms for the scheduling problem. Our parallel algorithms are portable across a wide range of parallel platforms. We report results on a set of high-level synthesis benchmarks on 8-processor SGI Origin and a 64 processor IBM SP-2. While some parallel algorithms for VLSI CAD reported by earlier researchers have reported a loss of qualities of results, our parallel algorithms produce exactly the same results as the sequential algorithms on which they are based.