Actor based parallel VHDL simulation using time warp
PADS '96 Proceedings of the tenth workshop on Parallel and distributed simulation
ICS '97 Proceedings of the 11th international conference on Supercomputing
Parallel Algorithms for Force Directed Scheduling of Flattened and Hierarchical Signal Flow Graphs
IEEE Transactions on Computers
A Comparison of Parallel Approaches for Algebraic Factorization in Logic Synthesis
IPPS '97 Proceedings of the 11th International Symposium on Parallel Processing
Simulated Annealing Based Parallel State Assignment of Finite State Machines
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Fine-Grained Parallel VLSI Synthesis for Commercial CAD on a Network of Workstations
ICPP '00 Proceedings of the Proceedings of the 2000 International Conference on Parallel Processing
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Combinational logic synthesis is a very important but computationally expensive phase of VLSI system design. Parallel processing offers an attractive solution to reduce this design cycle rime. In this paper we describe ProperMIS, a portable parallel algorithm for logic synthesis based on the MIS multi-level logic synthesis system. As part of this work, we have developed novel parallel algorithms for the different logic transformations of the MIS system. Our algorithm uses art asynchronous message-driven computing model with no synchronizing barriers separating phases of parallel computation. The algorithm is portable across a wide variety of parallel architectures, and is built around a well-defined sequential algorithm interface, so that we can benefit from future expansion of the sequential algorithm. We present results on several MCNC and ISCAS benchmark circuits for a variety of shared memory and distributed processing architectures. Our implementation produces speedups of an average of 4 on 8 processors.