Parallel Algorithms for Force Directed Scheduling of Flattened and Hierarchical Signal Flow Graphs
IEEE Transactions on Computers
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In this paper, we present some novel algorithms for scheduling hierarchical signal flow graphs in the domain of high-level synthesis. There are several key contributions of this paper. First, we develop a novel extension of the force-directed scheduling problem which naturally handles loops and conditionals by coming up with a scheme of scheduling {\em hierarchical} signal flow graphs. Second, we develop three new parallel algorithms for the scheduling problem. Third, our parallel algorithms are portable across a wide range of parallel platforms. We report results on a set of high-level synthesis benchmarks on 8-processor SGI Challenge and a network of 4 SUN SPARCstation5 work stations. Finally, while some parallel algorithms for VLSI CAD reported by earlier researchers have reported a loss of qualities of results, our parallel algorithms produce exactly the same results as the sequential algorithms on which they are based. Keywords: High-level synthesis,force-directed scheduling, hierarchical graphs,parallel algorithms,multiprocessors,network of workstations.