Dataflow-driven memory allocation for multi-dimensional signal processing systems
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Background memory area estimation for multidimensional signal processing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Integration, the VLSI Journal
Background memory management for dynamic data structure intensive processing systems
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Allocation of multiport memories for hierarchical data stream
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
MTDT '95 Proceedings of the 1995 IEEE International Workshop on Memory Technology, Design and Testing
Improved force-directed scheduling in high-throughput digital signal processing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast and extensive system-level memory exploration for ATM applications
ISSS '97 Proceedings of the 10th international symposium on System synthesis
Formalized methodology for data reuse exploration in hierarchical memory mappings
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
DAC '98 Proceedings of the 35th annual Design Automation Conference
Matisse: A System-on-Chip Design Methodology Emphasizing Dynamic Memory Management
Journal of VLSI Signal Processing Systems - Special issue on system level design
Journal of VLSI Signal Processing Systems - Special issue on system level design
Co-design of interleaved memory systems
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Memory aware compilation through accurate timing extraction
Proceedings of the 37th Annual Design Automation Conference
Memory binding for performance optimization of control-flow intensive behaviors
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low-power systems on chips (SOCs)
Proceedings of the conference on Design, automation and test in Europe
Code placement in hardware/software co-synthesis to improve performance and reduce cost
Proceedings of the conference on Design, automation and test in Europe
Access pattern based local memory customization for low power embedded systems
Proceedings of the conference on Design, automation and test in Europe
APEX: access pattern based memory architecture exploration
Proceedings of the 14th international symposium on Systems synthesis
Memory management for embedded network applications
Readings in hardware/software co-design
Access pattern-based memory and connectivity architecture exploration
ACM Transactions on Embedded Computing Systems (TECS)
HiPC '00 Proceedings of the 7th International Conference on High Performance Computing
Proceedings of the 40th annual Design Automation Conference
Layer Assignment echniques for Low Energy in Multi-Layered Memory Organisations
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Memory binding for performance optimization of control-flow intensive behavioral descriptions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic memory access management for high-performance DSP applications using high-level synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Embedded Systems Design
Using memory profile analysis for automatic synthesis of pointers code
ACM Transactions on Embedded Computing Systems (TECS)
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In this paper we present the problem of flow graph balancing for minimizing the required memory bandwidth. Our goal is to minimize the required memory bandwidth within the given cycle budget by adding ordering constraints to the flow graph. This allows the subsequent memory allocation and assignment tasks to come up with a cheaper memory architecture with less memories and memory ports. The effect of flow graph balancing is shown on an example. We show that it is important to take into account which data is being accessed in parallel, instead of only considering the number of simultaneous memory accesses. This leads to the optimization of a conflict graph.