Asynchronous transfer mode: solution for broadband ISDN
Asynchronous transfer mode: solution for broadband ISDN
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Dataflow-driven memory allocation for multi-dimensional signal processing systems
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Memory estimation for high level synthesis
DAC '94 Proceedings of the 31st annual Design Automation Conference
SMASH: a program for scheduling memory-intensive application-specific hardware
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Application-Driven Architecture Synthesis
Application-Driven Architecture Synthesis
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Synthesis from mixed specifications
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Fast and extensive system-level memory exploration for ATM applications
ISSS '97 Proceedings of the 10th international symposium on System synthesis
DAC '98 Proceedings of the 35th annual Design Automation Conference
A programming environment for the design of complex high speed ASICs
DAC '98 Proceedings of the 35th annual Design Automation Conference
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Memory arbitration and cache management in stream-based systems
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Codesign of embedded systems: status and trends
Readings in hardware/software co-design
Codesign of Embedded Systems: Status and Trends
IEEE Design & Test
The Cost of Communication Protocols and Coordination Languages in Embedded Systems
COORDINATION '02 Proceedings of the 5th International Conference on Coordination Models and Languages
System design tools for broadband telecom network applications
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Flow Graph Balancing for Minimizing the Required Memory Bandwidth
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Compiling for reconfigurable computing: A survey
ACM Computing Surveys (CSUR)
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Telecommunication network management applications often require application-specific ICs that use large dynamically allocated stored data structures. Currently available hardware synthesis environments typically do not support dynamic data structure concepts and their associated memory synthesis problems. In this paper we address the \fIbackground memory management\fP task in a hardware design trajectory, which includes allocation of a distributed memory architecture, assignment and mapping of abstract data structures to memories, and synthesis of dynamic management behavior. With this approach to optimal memory management and architecture exploration, the design entry point is lifted to a higher level than currently used for behavioral synthesis, as the specification can be a high-level program using data abstraction. The power of our approach will be substantiated on an industrial high-performance telecommunication ASIC design.