Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Scheduling using behavioral templates
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Interface co-synthesis techniques for embedded systems
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
ISDL: an instruction set description language for retargetability
DAC '97 Proceedings of the 34th annual Design Automation Conference
EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Flow Graph Balancing for Minimizing the Required Memory Bandwidth
ISSS '96 Proceedings of the 9th international symposium on System synthesis
RTGEN: An Algorithm for Automatic Generation of Reservation Tables from Architectural Descriptions
Proceedings of the 12th international symposium on System synthesis
Access pattern based local memory customization for low power embedded systems
Proceedings of the conference on Design, automation and test in Europe
New directions in compiler technology for embedded systems (embedded tutorial)
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Data and memory optimization techniques for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Code generation for embedded processors
ISSS '00 Proceedings of the 13th international symposium on System synthesis
MIST: an algorithm for memory miss traffic management
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Access pattern-based memory and connectivity architecture exploration
ACM Transactions on Embedded Computing Systems (TECS)
Data Memory Organization and Optimizations in Application-Specific Systems
IEEE Design & Test
Memory Architectures for Embedded Systems-On-Chip
HiPC '02 Proceedings of the 9th International Conference on High Performance Computing
Aggressive Memory-Aware Compilation
IMS '00 Revised Papers from the Second International Workshop on Intelligent Memory Systems
Proceedings of the 40th annual Design Automation Conference
RTGEN: an algorithm for automatic generation of reservation tables from architectural descriptions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Processor-memory coexploration using an architecture description language
ACM Transactions on Embedded Computing Systems (TECS)
Memory access driven storage assignment for variables in embedded system design
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Optimizing the memory bandwidth with loop fusion
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Proceedings of the 42nd annual Design Automation Conference
Zero cost indexing for improved processor cache performance
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Traversal caches: a first step towards FPGA acceleration of pointer-based data structures
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Processor Description Languages
Processor Description Languages
Embedded Systems Design
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Memory delays represent a major bottleneck in embedded systems performance. Newer memory modules exhibiting efficient access modes (e.g., page-, burst-mode) partly alleviate this bottleneck. However, such features can not be efficiently exploited in processor-based embedded systems without memory-aware compiler support. We describe a memory-aware compiler approach that exploits such efficient memory access modes by extracting accurate timing information, allowing the compiler's scheduler to perform global code reordering to better hide the latency of memory operations. Our memory-aware compiler scheduled several benchmarks on the TI C6201 processor architecture interfaced with a 2-bank synchronous DRAM and generated average improvements of 24% over the best possible schedule using a traditional (memory-transparent) optimizing compiler, demonstrating the utility of our memory-aware compilation approach.